Machine Learning Approach for Loop Unrolling

High Level Synthesis development flows rely on user-defined directives to optimize the hardware implementation of digital circuits. Nevertheless, the most beneficial directive values are hard to predict, and exhaustive explorations are infeasible even for moderately complex designs. Focusing on the Loop Unrolling directive, we herein address this challenge by proposing a novel Machine Learning methodology, able to jointly forecast the optimal loop unrolling factors for all the loops in a target application. We showcase that our method results in a better prediction score (up to 63%) and a reduced convergence time compared to other state-of-the-art approaches. Our method achieves 90% of the speedup that can be obtained (with a perfect a-priori knowledge of optimal loop unrolling factors) when synthesizing the computational hotspots of each considered benchmark as hardware accelerators.